IBM, ORNL and AMD launch quantum error-correction testbed: 120-qubit Nighthawk next to Umbra

IBM, the US Department of Energy's Quantum Science Center (QSC) at Oak Ridge National Laboratory (ORNL) and AMD announced a shared testbed for quantum error correction on 5 November 2026. It puts IBM's 120-qubit Nighthawk quantum processor in the same facility as ORNL's Umbra supercomputer, which is built from AMD Instinct MI355X GPUs and 5th Gen EPYC CPUs. The point is speed: error correction needs a classical computer to read the quantum chip's error signals and decide what to fix, and today that conversation usually crosses the internet.

Key points

• The platform co-locates IBM quantum computers, including the 120-qubit Nighthawk, with ORNL's Umbra HPC system at IBM's quantum site in Poughkeepsie, New York (IBM, ORNL and AMD press release).
• Umbra uses AMD Instinct MI355X GPUs and 5th Gen AMD EPYC CPUs; StorageReview reports that neither IBM nor AMD has published node counts, decoding latency or benchmarks.
• The work supports the DOE Quantum Genesis Mission's Q Competition goal of 100 logical qubits running 100,000 hard operations by late 2028; IBM's current experiments reach 70 logical qubits and 438 hard operations, a gap of roughly 230 times in operation count.
• IBM says lessons may inform IBM Quantum Starling, its planned first fault-tolerant quantum computer; the announcement gives no schedule for outside access.

What happened

The three partners described the system as a "co-design platform for quantum error correction". The first deployment pairs IBM's quantum computers, including Nighthawk, IBM's most powerful processor by its own description, with Umbra. The press release says the AMD hardware "provides the classical computing foundation" for research into error correction, decoder optimisation and software orchestration. The Register reports the platform also includes AMD Versal adaptive chips for low-latency control, readout and decoding of the quantum circuitry. AMD's own post lists Versal chips among the technologies it offers for that job "near the quantum processor" but does not say they are part of Umbra, and StorageReview notes the announcement does not place them there, so treat that detail as The Register's reading.

Planned extensions: the platform will connect to the Oak Ridge Leadership Computing Facility in Tennessee, and ORNL also describes a link to Lux, its AMD-based supercomputer (per StorageReview and The Register). StorageReview points out that these links are described as planned and that no completion date or external-access schedule was given.

Researchers will be able to use IBM's Quantum System API, which, in the press release's words, lets them measure qubits mid-calculation and act on the result in real time, set the exact timing of the signals that protect qubits from noise, and work with raw measurement signals.

Background

Quantum bits are fragile. Error correction spreads one logical qubit across many physical qubits and repeatedly checks them for signs of trouble. A classical computer must then work out which physical qubits went wrong, a job IBM calls decoding, and it must keep pace with the quantum chip. Today, StorageReview notes, quantum computers and HPC clusters rarely sit in the same building, so researchers reach the quantum machine through the cloud and join the two halves through separate software interfaces, with delay at every handoff.

The new platform is part of a longer line of collaboration. According to the press release, IBM and ORNL already work through the QSC, an ORNL-led DOE research centre, and earlier this year showed workloads split between quantum computers and the Frontier supercomputer to simulate magnetic materials and a candidate fusion-fuel material. IBM and AMD demonstrated last year an algorithm that decodes quantum errors efficiently on AMD chips, and IBM uses AMD GPUs in a quantum-centric workflow called sample-based quantum diagonalization.

The numbers

The government target is the yardstick the partners chose. The press release says the Q Competition, announced under the DOE's Quantum Genesis Mission, targets 100 logical qubits running 100,000 hard operations by late 2028. IBM's own figures for current work are 70 logical qubits and 438 hard operations, which it says are listed on the Quantum Advantage Tracker.

type: bar
title: Hard operations on logical qubits: IBM's current experiments vs the Q Competition target
unit: hard operations
source: IBM, ORNL and AMD press release (5 Nov 2026)
highlight: Q Competition target (late 2028)
IBM current experiments (70 logical qubits) | 438
Q Competition target (100 logical qubits, late 2028) | 100000

The partners' own arithmetic is that closing the gap "means the field needs to achieve a roughly 230-fold increase in hard operation count." On the qubit side the distance is smaller, from 70 to 100 logical qubits. The Register describes the Q Competition goal differently, as a system with 100 logical qubits "capable of performing hundreds of millions of fault-tolerant operations"; this article uses the press release's figure, which IBM, ORNL and AMD issued themselves, and the discrepancy is unexplained.

IBM also puts a research number on the hierarchical error-correction approach the platform can explore. An inner code protects qubits within a module, and an outer code wraps the inner code's logical qubits for a second layer. IBM research suggests that approach could reach a trillion logical operations at a physical error rate of one in a thousand. That is a projection from IBM's research, not a measurement on this machine.

What it means

For researchers, the practical gain is lower latency and fewer moving parts. Decoders can be trained and tested on the MI355X GPUs while the quantum chip is running, and programs can branch on mid-circuit measurements without a trip over the internet. The platform lets teams compare what each method costs in qubits, time, samples and classical computing, and see where GPUs help most.

For AMD, the announcement ties its data-centre GPUs and CPUs to the quantum roadmap. AMD's chief technology officer Mark Papermaster is quoted calling it "an important step toward building the scalable, efficient computing infrastructure needed to make fault-tolerant quantum computing a reality."

For the wider field, the message from IBM's research director Jay Gambetta is that the question has moved. In the press release he said it is no longer whether error correction works on quantum hardware but how to speed it up and optimise it so scientists can use it. Read that as IBM's framing: the public targets show the remaining distance is large.

What we don't know yet

• How big Umbra is. Neither IBM nor AMD has published node counts, GPU or CPU quantities, decoding-latency figures or benchmarks for this deployment (StorageReview).
• When outside researchers can get access, and on what terms.
• When the planned links to the Oak Ridge Leadership Computing Facility and Lux will be completed.
• Whether the Q Competition goal is the 100,000 operations the press release states or the larger figure The Register used.
• Whether the Versal control chips The Register mentions are part of the system; AMD's post lists them as a capability, not a confirmed component.

What to watch next

Look for published decoding-latency numbers and the first papers using the platform, and for updates to the Quantum Advantage Tracker where IBM lists its logical-qubit experiments. The Q Competition's interim milestones on the way to late 2028 will show whether the 230-fold gap in operation count is closing. Also watch for IBM's progress toward Starling, its fault-tolerant machine, which the press release says this work may inform.

Sources

• Oak Ridge National Laboratory, IBM and AMD launch new co-design platform for quantum error correction (press release, via The Quantum Insider)
• Oak Ridge labs gets hybrid quantum-HPC system to test qubit error correction (The Register)
• IBM, ORNL and AMD co-locate the 120-qubit Nighthawk with an MI355X Umbra cluster (StorageReview)
• AMD builds the classical foundation for quantum's future (AMD Newsroom)