AMD EPYC 9006 Venice: 256 Zen 6 cores, 600 W, 5.3 GHz EPYC 9686F, SPECrate 5,470
AMD's 6th Gen EPYC (Zen 6, SP7) is shipping with up to 256 cores per socket; the performance numbers so far are AMD's own.
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AMD launched its 6th Gen EPYC server processors on 10 November 2026: the EPYC 9006 series, code-named Venice, built on the new Zen 6 core. The top part, the EPYC 9996, has 256 cores and 512 threads in a single socket, a 600 W power budget and a list price AMD gives as $14,904. AMD says systems are shipping from server makers now, with Microsoft Azure and Oracle Cloud Infrastructure instances "generally available soon". Most of the performance numbers so far come from AMD itself, so this article separates what the company claims from what independent reviewers have published.
Key points
- The EPYC 9006 series (Zen 6, socket SP7) tops out at 256 cores and 512 threads per socket, up from 192 cores in the EPYC 9005 generation.
- The flagship EPYC 9996 has a 600 W "Default CPU Power" and a listed price of $14,904, according to AMD's footnotes.
- AMD says a dual-socket EPYC 9996 system scores 5,470 on SPECrate 2017_int_base, up to 2.2x an Intel Xeon 6980P system, with 2.0x the performance per dollar.
- The 96-core EPYC 9686F reaches 5.3 GHz boost, raised from the 5.0 GHz announced earlier, per ServeTheHome.
- A cache-stacked EPYC "X" part (Venice-X) is planned for the second half of 2027, according to The Register.
What happened
AMD's announcement covers the 6th Gen EPYC server family on the SP7 socket and a 6th Gen EPYC Embedded line. The company says the processors are shipping to its server partners, that Meta is the lead customer validating platforms ahead of large-scale deployment, and that Azure (HDv2 in preview, HXv2, and ND MI455X v7 built on AMD's Helios rack) and OCI (Compute E7) will offer instances. AMD also changed how it quotes power: it now uses "Default CPU Power", which it says covers compute and I/O dies together, instead of TDP.
ServeTheHome's launch-day piece lists nine launch SKUs. The top of the range:
- EPYC 9996: 256 cores / 512 threads, 4.1 GHz boost, 2.55 GHz base, 1,024 MB L3, 600 W.
- EPYC 9966: 192 cores / 384 threads, 4.0 GHz boost, 768 MB L3, 600 W.
- EPYC 9756: 128 cores, 4.0 GHz boost, 512 MB L3, 500 W.
- EPYC 9686F: 96 cores, 5.3 GHz boost, 3.4 GHz base, 384 MB L3, 500 W.
- EPYC 9586F: 64 cores, 5.0 GHz boost, 500 W.
One discrepancy worth knowing: AMD's own text says the high-frequency host-node part reaches "up to 5.3 GHz", while a footnote in the same release describes a 96-core, 5 GHz part. ServeTheHome explains the difference: the 9686F's clock was raised from 5.0 GHz after final silicon exceeded AMD's expectations. We use 5.3 GHz here on that basis. AMD's footnotes also name an "EPYC 9965" with 384 cores in a two-socket system, which does not match ServeTheHome's SKU table (which lists a 9966 at 192 cores); we have left the 9965 figures out.
Background
EPYC's recent generations each raised the core count and power budget. ServeTheHome's comparison table puts the progression like this: EPYC 9004 (Genoa, Zen 4, 5 nm) topped out at 128 cores with 12 channels of DDR5-4800; EPYC 9005 (Turin, Zen 5) reached 192 cores with DDR5-6400; EPYC 9006 (Venice, Zen 6, listed as 2 nm by ServeTheHome; AMD's release does not state the process) reaches 256 cores with 16 channels of DDR5-8000 or MRDIMM-12800, up to 8 TB of memory, and PCIe 6.0. Peak power rose from 400 W to 500 W to 600 W over the same three generations. AMD says Venice has 33% more cores than Turin and about 20% higher instructions per clock, and the core complex grew to 32 cores with 128 MB of cache, up from 16 cores and 32 MB.
| cores | |
|---|---|
| EPYC 9004 | 128 |
| EPYC 9005 | 192 |
| EPYC 9006 | 256 |
Source: ServeTheHome, EPYC 9006 launch coverage
AMD's position is also stronger than it was. ServeTheHome reports that AMD holds about 46% of x86 server CPU revenue share and expects Venice to push it past 50% for the first time, and that AMD's data center division is on course to surpass Intel's in revenue this quarter. Both are the outlet's reporting of AMD's own figures, not independent market data.
The numbers
AMD's headline benchmark is SPECrate 2017_int_base on dual-socket systems. The company's published comparison:
On those numbers AMD claims up to 2.2x the performance of a Xeon 6980P system (256 cores in two sockets, 500 W, $13,955 per AMD's footnote) and 2.0x performance per dollar, and up to 3.7x an Nvidia Vera system. The Vera and Arm AGI scores are AMD's own estimates, and the comparison against the Xeon 6990E+ (576 cores in two sockets) uses Intel's efficiency-core part, so it is a different kind of chip. AMD also claims up to 1.8x LLM output throughput for its host-node processors versus the previous generation (a model-weight CPU-offload test with Qwen3-30B-A3B on an Nvidia B200), and about 3.3x more AI-agent sandboxes per CPU watt than Vera. ServeTheHome had no benchmark results in its launch-day article; it says its tests of the 9996 and a "lot more content" will follow. Treat all performance figures as vendor claims until those arrive.
What it means
For data-centre buyers, the case AMD is making is density: 256 cores per socket means fewer servers for the same core count, but at 600 W per socket the cooling and rack-power budget matters as much as the CPU price. AMD's own rack example is an agent-hosting workload where it says lowering the power limit by 15% costs about 1% of per-server performance and fits about 1.18x more agents in a 35 kW rack.
For AI infrastructure, AMD is pitching EPYC as the CPU that runs the agents themselves, not just the host for GPUs. Its Helios rack pairs 18 96-core Venice CPUs with 72 MI455X GPUs, a 1:4 ratio, according to The Register. A related chip, Verano, is a non-socketed, soldered CPU with 72 high-frequency or 192 density cores and LPDDR5X memory, designed for AMD's next rack-scale systems with the MI500X GPU; The Register reports it shipping next year and notes that AMD has not said what CPU-to-GPU ratio it targets.
For HPC and chip design, the cache-stacked Venice-X is the part to wait for. The Register reports up to 96 cores, 1,152 MB of L3 per socket and 5.3 GHz clocks (against 3.7 GHz for Genoa-X), with shipments starting in the second half of 2027. AMD's Madhu Rangarajan told the outlet "For the first time, you can get the larger L3 in our highest frequency part." Venice-X does not raise core count or total cache over Genoa-X, the outlet notes; the gain is clock speed.
What we don't know yet
- Independent benchmarks: none had been published at the time of writing.
- Pricing beyond the two SKUs in AMD's footnotes.
- Which AMD process node is used, since AMD's release does not say.
- The SP8 platform, which ServeTheHome says is a more restrained design arriving early next year.
- Real-world power draw at 600 W under mixed loads, and which OEM systems ship first.
What to watch next
Watch for ServeTheHome and other independent reviewers' full test results, Intel's response in its Xeon roadmap, cloud availability dates for Azure and OCI, and the first Venice-based instances for AI inference. Also watch whether AMD publishes its full footnote set with corrected SKU names. Our earlier Veeam KB4960 kernel-panic report on EPYC is a reminder that new server silicon also brings software compatibility issues.
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